情報科学部Faculty of Computer and Information Sciences
OTR100KA-CS-200（その他 / Others 100）プロジェクト（春）Project
李 亜民Yamin LI
授業コードなどClass code etc
| 学部・研究科Faculty/Graduate school | 情報科学部Faculty of Computer and Information Sciences |
| 添付ファイル名Attached documents | |
| 年度Year | 2023 |
| 授業コードClass code | J0610 |
| 旧授業コードPrevious Class code | |
| 旧科目名Previous Class title | |
| 開講時期Term | 春学期授業/Spring |
| 曜日・時限Day/Period | 金3/Fri.3 |
| 科目種別Class Type | |
| キャンパスCampus | 小金井 / Koganei |
| 教室名称Classroom name | 各学部・研究科等の時間割等で確認 |
| 配当年次Grade | 2～3 |
| 単位数Credit(s) | 1 |
| 備考（履修条件等）Notes | |
| 他学部公開科目Open Program | |
| 他学部公開（履修条件等）Open Program (Notes) | |
| グローバル・オープン科目Global Open Program | |
| 成績優秀者の他学部科目履修制度対象Interdepartmental class taking system for Academic Achievers | |
| 成績優秀者の他学部科目履修（履修条件等）Interdepartmental class taking system for Academic Achievers (Notes) | |
| 実務経験のある教員による授業科目Class taught by instructors with practical experience | |
| SDGsCPSDGs CP | |
| アーバンデザインCPUrban Design CP | |
| ダイバーシティCPDiversity CP | |
| 未来教室CPLearning for the Future CP | |
| カーボンニュートラルCPCarbon Neutral CP | |
| 千代田コンソ単位互換提供（他大学向け）Chiyoda Campus Consortium | |
| 選択・必修Optional/Compulsory | |
| カテゴリー（2022年度以降入学者）Category (2022~) | |
| カテゴリー（2021年度以前入学者）Category (~2021) | |
| カテゴリーCategory |
専門教育科目 専門科目 |
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Outline (in English)
The course focuses on computer hardware design and implementation. Students will study the following contents.
1. Verilog HDL (Hardware Description Language)
2. EDA (Electronic Design Automation) Tools (ModelSim and Intel Quartus II)
3. Combinational Circuit Design in Verilog HDL
4. Sequential Circuit Design in Verilog HDL
5. Input / Output Interface Controller Design in Verilog HDL
6. CPU Design in Verilog HDL
7. Computer Design in Verilog HDL
8. Computer System Design in Verilog HDL
Students will be expected to spend more than four hours to study each theme.
Evaluated based on the class participation (10%), progress of projects (60%), report (20%), and presentation (10%).
授業で使用する言語Default language used in class
日本語 / Japanese
授業の概要と目的（何を学ぶか）Outline and objectives
The course focuses on computer hardware design and implementation. Students will study the following contents.
1. Verilog HDL (Hardware Description Language)
2. EDA (Electronic Design Automation) Tools (ModelSim and Intel Quartus II)
3. Combinational Circuit Design in Verilog HDL
4. Sequential Circuit Design in Verilog HDL
5. Input / Output Interface Controller Design in Verilog HDL
6. CPU Design in Verilog HDL
7. Computer Design in Verilog HDL
8. Computer System Design in Verilog HDL
到達目標Goal
We know "System Engineer (SE) = Software Engineer (SE) + Hardware Engineer (HE)", in the field of computer science and engineering. If you want to be a Professional System Engineer in future, you must know about the hardware design. Through this project, students can design various hardware circuits, including CPUs, in Verilog HDL, implement the circuits on FPGA, and prepare beautiful technical reports.
この授業を履修することで学部等のディプロマポリシーに示されたどの能力を習得することができるか（該当授業科目と学位授与方針に明示された学習成果との関連）Which item of the diploma policy will be obtained by taking this class?
情報科学部ディプロマポリシーのうち「DP3-1」と「DP4-3」に関連
授業で使用する言語Default language used in class
日本語 / Japanese
授業の進め方と方法Method(s)（学期の途中で変更になる場合には、別途提示します。 /If the Method(s) is changed, we will announce the details of any changes. ）
The contents include the Verilog HDL grammar, module structure, combinational and sequential circuits design, LED, buttons, switches, seven-segment LEDs in FPGA board, VGA (Video Graphics Array), keyboard, scan code, ASCII and Kanji fonts, CPU, and assembly programming language. We prepare some samples and students challenge their own codes in the class. Finally, each student will have a presentation and submit a technical report written with LaTeX. In addition to the projects, the third-year students will read research papers and present the papers. Feedbacks: At the beginning of each lecture, the previous exercise problems will be explained.
アクティブラーニング（グループディスカッション、ディベート等）の実施Active learning in class (Group discussion, Debate.etc.)
あり / Yes
フィールドワーク（学外での実習等）の実施Fieldwork in class
なし / No
授業計画Schedule
授業形態/methods of teaching：対面/face to face
※各回の授業形態は予定です。教員の指示に従ってください。
1[対面/face to face]：Introduction
Introduction to research and projects
2[対面/face to face]：Basic of Verilog HDL
Verilog HDL, Module, Test Bench, EDA Tools, Switch, Button, LED.
Implementation on DE0-CV with Quartus II
3[対面/face to face]：Styles of Verilog HDL
Structural Style, Dataflow Style, Behavioral Style, Multiplexer
4[対面/face to face]：Verilog HDL Operators
Verilog HDL Operators, ALU
5[対面/face to face]：Verilog HDL Statements
Always and Function, If-Else and Case, Seven-Segment LED
6[対面/face to face]：Verilog HDL Registers
Module Invocation, Counter
7[対面/face to face]：Digital Clock
Digital Clock
8[対面/face to face]：VGA Display Controller
VGA Display Controller, ASCII Font Table, Kanji
9[対面/face to face]：PS2 Keyboard Controller
PS2 Keyboard Controller
10[対面/face to face]：RISC-V CPU Design
RISC-V CPU, Scancode
11[対面/face to face]：Assembly Programming (1)
Assembly Programming, Scancode to ASCII
12[対面/face to face]：Assembly Programming (2)
Assembly Programming, Scancode to ASCII
13[対面/face to face]：Documentation with Latex
Documentation with Latex
14[対面/face to face]：Presentation
Presentation and Report Submission
授業時間外の学習（準備学習・復習・宿題等）Work to be done outside of class (preparation, etc.)
1. Learning activities outside of classroom: 4 hours per week
2. Study Verilog HDL
3. Design circuits with EDA tools
テキスト（教科書）Textbooks
Online materials
参考書References
成績評価の方法と基準Grading criteria
Evaluated based on the class participation (10%), progress of projects (60%), report (20%), and presentation (10%)
学生の意見等からの気づきChanges following student comments
Prepared more sample Verilog HDL codes
学生が準備すべき機器他Equipment student needs to prepare
Bring your note PC to the class