情報科学研究科Graduate School of Computer and Information Sciences
COT500K1（計算基盤 / Computing technologies 500）Advanced Computer ArchitectureAdvanced Computer Architecture
コンピュータアーキテクチャ特論
李 亜民Yamin LI
授業コードなどClass code etc
| 学部・研究科Faculty/Graduate school | 情報科学研究科Graduate School of Computer and Information Sciences |
| 添付ファイル名Attached documents | |
| 年度Year | 2022 |
| 授業コードClass code | TZ003 |
| 旧授業コードPrevious Class code | |
| 旧科目名Previous Class title | |
| 開講時期Term | 春学期授業/Spring |
| 曜日・時限Day/Period | 木2/Thu.2 |
| 科目種別Class Type | |
| キャンパスCampus | 小金井 |
| 教室名称Classroom name | 各学部・研究科等の時間割等で確認 |
| 配当年次Grade | |
| 単位数Credit(s) | 2 |
| 備考（履修条件等）Notes | |
| 実務経験のある教員による授業科目Class taught by instructors with practical experience | |
| カテゴリーCategory |
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授業の概要と目的（何を学ぶか）Outline and objectives
Most modern CPUs can exploit 3-level parallelism: (1) The CPUs can dispatch multiple instructions from an instruction stream in every clock cycle to exploit the instruction-level parallelism (ILP). (2) The CPUs can execute multiple threads simultaneously to exploit the thread-level parallelism (TLP). And (3) There are multiple cores in a single CPU chip so that it can execute multiple programs in parallel to exploit the job-level parallelism (Chip multiprocessors). To achieve high-performance in scientific computations, Wallace Tree, Goldschmidt algorithms and Newton-Raphson algorithms are used to speedup the operations of the multiplications, division, and square root. For computer/CPU design, the Verilog HDL (Hardware description language) is widely used by both academia and industry. For the supercomputer design, the low-cost high-performance interconnection networks are required. This lecture will cover all the contents mentioned above.
到達目標Goal
Through this lecture, students will learn how to design high-performance CPU/computer in Verilog HDL, including ALU, FPU, caches, TLB, MMU, and I/O interface. After finishing the lecture, students should become a professional in Verilog HDL and in CPU designs.
この授業を履修することで学部等のディプロマポリシーに示されたどの能力を習得することができるか（該当授業科目と学位授与方針に明示された学習成果との関連）Which item of the diploma policy will be obtained by taking this class?
Among diploma policies, "DP1" and "DP2" are related.
授業で使用する言語Default language used in class
英語 / English
授業の進め方と方法Method(s)（学期の途中で変更になる場合には、別途提示します。 /If the Method(s) is changed, we will announce the details of any changes. ）
The contents of the lecture include technology and performance evaluation, instruction architectures, pipelining, floating point adder design, Wallace Tree, Goldschmidt algorithms, Newton-Raphson algorithms, FPU/CPU design, multithreading/multicore CPU design, cache and TLB design, PS/2 Keyboard and mouse, VGA controller, and interconnection networks. In the last class, students will present their work related to this course.
アクティブラーニング（グループディスカッション、ディベート等）の実施Active learning in class (Group discussion, Debate.etc.)
なし / No
フィールドワーク（学外での実習等）の実施Fieldwork in class
なし / No
授業計画Schedule
授業形態/methods of teaching：対面/face to face
※各回の授業形態は予定です。教員の指示に従ってください。
1[未定/undecided]：Performance Evaluation
Introduction, computer performance evaluation, and RISC-V
2[未定/undecided]：RISC-V ISA and CPU Design
RISC-V instruction set architecture and RISC-V RV32IM CPU design
3[未定/undecided]：Pipelining
Pipelined RISC-V RV32IM CPU design
4[未定/undecided]：Floating Point Adder Design
IEEE 754 floating-point formats, FPU addition and subtraction
5[未定/undecided]：Wallace Tree
Multiplication and Wallace Tree Circuit
6[未定/undecided]：Goldschmidt Algorithms
Goldschmidt division and square root algorithms
7[未定/undecided]：Newton-Raphson Algorithms
Newton-Raphson division and square root algorithms
8[未定/undecided]：FPU/CPU Design
RISC-V CPU/FPU (floating-point unit) design
9[未定/undecided]：Memory and Cache
Memory, memory hierarchy, cache, and RISC-V CPU design with caches
10[未定/undecided]：Memory Management and TLB
MMU, TLB, and RISC-V CPU design with TLBs
11[未定/undecided]：Multithreading and Multicore CPU
Multithreading and multicore RISC-V CPU design
12[未定/undecided]：Input and Output Systems
Memory-mapped I/O, keyboard and mouse, and VGA controller
13[未定/undecided]：High-performance computing
Supercomputers and interconnection networks
14[未定/undecided]：Presentations
Present your theme
授業時間外の学習（準備学習・復習・宿題等）Work to be done outside of class (preparation, etc.)
Write Verilog HDL codes for CPU/computer system design and prepare presentation slides. On average, it takes four hours to finish weekly assignments.
テキスト（教科書）Textbooks
Online materials
参考書References
1. Computer Architecture: A Quantitative Approach, Sixth Edition, John L. Hennessy and David A. Patterson, Morgan Kaufmann Publishers, Inc. 2017.
2. Computer Principles and Design in Verilog HDL, Yamin Li, John Wiley & Sons, ISBN 978-1-118-84109-9, 2015.
成績評価の方法と基準Grading criteria
1. Participation and discussion: 40%
2. Presentation: 60%
学生の意見等からの気づきChanges following student comments
None
学生が準備すべき機器他Equipment student needs to prepare
Bring note-PC to the lecture